Convert connectors to fast connectors.
According to the location of the connection equipment distribution module. Can be isolated to obtain DC24/48/100V, AC100/200V input signal.DC input.
Number of input channels: 2Ch.
DC5/12/24V input.
Maximum count rate: pulse/s 200k.
Linear counter function.
Ring counter function LJ61CL12.
Uniform output function.
Preset function.
Count invalid function.
Latch counter function LJ61CL12
Sampling counter function.
Periodic pulse counter function.
Flexibly applied to various applications
Combination of functions,
Easy to achieve speed measurement, long measuring function, the single pulse output, the ratio of the set / distribution output, PWM control, cam switch control, such as a wide range of control LJ61CL12.
Single pulse.
To trigger the input as a starting point, with a minimum 25ns unit to adjust the ON/OFF time.
The action time deviation of ON/OFF is ns level, so it can achieve high precision control.
Velocity measurement and length measurement
In addition to the measurement of ON width and OFF width,
Can also achieve different sensor ON time difference and other conditions of the measurement LJ61CL12.
The high precision measurement of the smallest 25ns unit can be realized.
Delayed output
The output time delay of each channel can be adjusted so that the error output can be realized. Input and output (DC/ differential).
Input points: 12 points (DC5V/DC24V/ differential universal).
Pulse input speed: the highest pulse/s 8M (2MHz).
Output points: 8 points (DC5V ~ DC24V) 6 points (differential).
Pulse output speed: the highest pulse/s 8M (2MHz).
High speed and stable input / output response
The high speed response can be achieved without the CPU module''s operation and bus performance,
Stable input and output response through hardware processing.
LD40PD01 is equipped with an external input and output interface and FPGA,
Therefore, high speed control can be realized without the influence of the scanning time of the CPU module and the bus performance (the input and output response time of the s instruction is realized).
Can achieve stable input and output response (proocessing time of the deviation of the ns level) LJ61CL12.
Through the intuitive tools for FPGA settings.
In the FPGA design process can be omitted in the past must be designed to deal with (HDL description, logic synthesis and time verification),
Reeduce working hours LJ61CL12. After receiving the product can be used immediately to verify the use of special tools, can significantly shorten the design time.