Input points: 32 points.
Input voltage: DC24V.
Enter the public side of the way: 32 points / public.
Output form: transistor output (source).
Output points: 32 points.
Rated output voltage: DC12 ~ 24V.
Max load current: 0.1A/1 point.
Protection function: have
Output common way: 32 point / common.
Input / output occupied points: 32 points (I/O distribution: input and output mixed 32 points) FA-TH16YTR20S FA-TH16YTR20S
External wiring connection: 40 pin connector two.
1, the switch quantity acquisition and switch control and RS-485 bus are isolated from each other, and isolated from the whole system.
2, the power supply line has anti reverse connect function, once the wrong power line,
Will automatically cut off the power to protect the entire module is not damaged FA-TH16YTR20S.
With over-voltage protection function, when the voltage is too high, automatic disconnection,
Protecting the entire module is not damaged.
3, RS-485 interface with 600W lightning protection and surge protection function, with 3000V photoelectric isolation.
4, the use of Modbus protocol, good general, can be very convenient and other systems,
Customers can also according to their own personal needs, custom related agreements, convenient and flexible FA-TH16YTR20S.
5, communication lines using RS-485 bus, support for multiple modules in parallel use,
Easy to expand the system, good scalability. Input and output (DC/ differential).
Input points: 12 points (DC5V/DC24V/ differential universal).
Pulse input speed: the highest pulse/s 8M (2MHz).
Output points: 8 points (DC5V ~ DC24V) 6 points (differential).
Pulse output speed: the highest pulse/s 8M (2MHz).
High speed and stable input / output response
The high speed response can be achieved without the CPU module''s operation and bus performance,
Stable input and output response through hardware processing.
LD40PD01 is equipped with an external input and output interface and FPGA,
Therefore, high speed control can be realized without the influence of the scanning time of the CPU module and the bus performance (the input and output response time of the s instruction is realized).
Can achieve stable input and output response (processiing time of the deviation of the ns level) FA-TH16YTR20S.
Through the intuitive tools for FPGA settings.
In the FPGA design process can be omitted in the past must be designed to deal with (HDL description, logic synthesis and time verification),
Reeduce working hours FA-TH16YTR20S. After receiving the product can be used immediately to verify the use of special tools, can significantly shorten the design time.